Many devices are currently integrated on a single die or chip. These devices are arranged in various configurations on the chip. The arrangement of the devices is referred to as a layout. Typically, the layout includes active areas with devices and inactive areas which are not used for devices. For example, a memory chip comprises densely packed arrays of transistors and storage nodes (memory cells), and loosely packed transistors (support circuitry), built-in fuses, bond pads and the like. The devices are connected to each other by means of conductive lines to form integrated circuits. As such, the overall chip layout includes areas having densely packed, complex arrays of devices, areas with less densely packed devices, and other areas that have no devices. Areas on the chip that are not occupied by electrically functional structures might be filled with electrically inactive unpatterned areas for planarization purposes. The resulting chip thus has several areas, some of which have a much higher pattern density than other areas. The size of devices on a single chip can also vary widely as well.
It is known that certain processing steps, such as etching, do not occur uniformly across a substrate, particularly when the number and placement of devices in an integrated circuit varies and the pattern density changes from one area of the integrated circuit to another. This phenomenon is well known as loading variation. Loading variation causes variations in the dimension of the resulting features and spaces that form the devices.
As design rules become smaller, e.g., to 0.25 micron and lower, variations in dimension caused by loading variation become more problematic. Variations in dimension across the chip or more commonly referred to as across chip linewidth variation (ACLV) causes timing control problems that negatively affect chip performance. Additionally, ACLV even affects the less densely Kerf areas where test structures and probe pads are placed for process monitoring. Variations in dimension of the test structures make it difficult to accurately monitor the manufacturing process of the chip.
ACLV as a result of loading principally depend upon the pattern density of surrounding features during an etch step or the pattern factor of the layer or material being etched. Pattern factor is defined as the ratio of patterned and unpatterned areas. Openings in areas of high pattern density tend to etch more anisotropically, producing openings with vertical sidewalls. When etching occurs in low pattern density areas, more deposits form on the sidewalls of the opening as etching continues, and the sidewalls produced are generally more tapered. Tapered openings cause linewidth variations from the top to the bottom of features, and produce a different "footprint", e.g., the opening is larger or smaller at a particular depth of etch, as shown in FIG. 1. In FIG. 1, opening 10 has been etched more anisotropically, producing an opening to the substrate 14 that has straight sidewalls and a particular dimension d1 that is uniform at any depth of etch.
Opening 20 has been etched with a slight taper, resulting in a smaller diameter opening at the substrate 14 than at the top. Thus the dimension d2 of the opening 20 is variable, and the "footprint" or diameter at the substrate 14 is not the same for opening 10 and opening 20, even though the diameter of the openings in the etch mask used to make them are the same. Thus the size or dimension of the openings in the etched layer can vary across the substrate. Such variations in dimensions can exceed specified tolerances, adversely affecting yield.
From the above discussion, it is desirable to avoid variations in dimension across the chip.